The present invention relates, in general, to Silicon on Insulator (SOI) devices, and more particularly to a method for forming isolation structures between SOI devices.
SOI Field Effect Transistor (FET) devices are similar to FET devices formed in bulk silicon in that they both have a source, a drain, and a gate structure. SOI devices, however, are formed in a substrate which has a buried isolation region formed below the FET. The buried isolation region is typically formed by implanting the silicon substrate with oxygen to create a silicon dioxide region which is commonly referred to as the Separation by Implantation of Oxygen (SIMOX) process. The buried isolation region reduces or eliminates many of the parasitic problems common to FET devices made in bulk silicon.
Although the buried isolation region does eliminate the need for implanted wells to isolate devices, it is still necessary to form isolation structures between neighboring devices. One previously known technique is to form trench structures by etching away a portion of the silicon substrate between devices and perhaps filling that portion with a non-conductive substance. Unfilled trench structures, however, can present a step coverage problem since the surface of the substrate is no longer planar. The trench structures are also difficult to form and are also difficult to fill.
An alternative approach is the common Localized Oxidation of Silicon (LOCOS) technique. A silicon dioxide and silicon nitride layer are formed on the substrate and the silicon nitride layer is selectively patterned and etched. The substrate is then oxidized through the exposed portion of the silicon dioxide layer since the silicon nitride layer acts as an oxidizing barrier. This technique leads to a large encroachment of field oxide which can result in thinned silicon active areas along the device edge and low edge threshold voltage. A polysilicon buffer layer can be added to the oxidation stack to reduce the encroachment. The thicker field oxide required with Poly-Buffered LOCOS (PBL), however, results in stress-induced dislocations and increased device leakage. The PBL isolation structure also results in a non-planar structure.
Accordingly, it would be advantageous to have a method for forming an isolation structure that not only isolates neighboring devices in the SOI substrate, but does so while maintaining a small encroachment and leaving the surface of the substrate relatively planar. It would be of further advantage to provide a method for forming an isolation structure that has reduced stress during oxidation and thus reduces stress-induced leakage.